Macro Modeling and Verification Engineer
Job Description. More>>
Works with RTL team, circuit design team and implementation team to define, model and verify the macros of AMD's next high speed microprocessor.
Responsibilities include writing and debugging high level Verilog model of macro, writing testbench code to verify correct function of the model and verifying that the function of the gate level netlist matches the function of the Verilog model. Will read and interpret transistor level schematics, write and debug Verilog code, optimize Verilog code for simulation performace, run formal equivalence tools such as Verplex's LEC to compare model with schematic and write testbench code in Verilog to exercise both the Verilog model and theschematic model.
Desired Profile
Should have strong logic and/or digital custom circuit design experience. Should have experience with Verilog or other high level programming language. Must be able to quickly understand a logical function and devise a means to test both the obvious functionality and the undocumented boundary conditions. Bachelors in EEE/ECE is required. Masters is preferred.
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