OPENINGS @ ATRENTA

Employment at Atrenta - Open Positions (US & Other Countries)
Position Title - Genesis Product Applications EngineerLocation - San Jose, CA or Texas, United States
Profile of the Candidate
Atrenta is seeking a candidate with a minimum of 5+ years experience with SoC front-end design tools and application technology. The successful candidate will posses industry experience in system architecture, design and chip assembly concepts and hands-on experience in SystemC or similar modeling. The candidate should also have a good understanding of either Verilog or VHDL hardware description languages and have solid communication skills.
Job Description
Assist in closing business by providing technical aid and support during various stages of the sales cycle - both pre and post-sales. Perform customer discovery and qualification, product demonstrations and evaluations, answer inquiries, and generally assure prospective customer is exposed to the full capabilities and benefits of products specific to their application.
Post-sales support is a very important component of this assignment. These engagements will be limited to a small number of top-tier semiconductor systems companies.Ongoing business will be driven largely by continuing to grow relationships and opportunities with those companies.
Provide expert technical assistance to customers, other application engineers, distributors, and third party vendors.
Contribute to product technical direction, develop applications, and applications notes.Write articles and white papers to further product usability, adoption and proliferation.
Develop and deliver customer training programs, tutorials, and seminars.
Review and edit technical documentation, release notes, and user guides.
Perform and document customer benchmarks and competitive comparisons.
Participate in and drive Beta testing and provides feedback to R&D.
Develop and present product demonstrations for industry trade shows (DAC).
Work closely with Atrenta Customer Support to ensure a positive experience with Atrenta products including: logging bugs, tracking and driving bug fixes and enhancements with R&D.
Develop personal rapport with key technologists at current and prospective customers.
Job Requirements
BSEE Computer Science/ Electrical Engineering/ Computer Engineering; MSEE preferred
Minimum 5 years experience as a Field AE in the EDA industry
Lead Chip design engineer or part of a chip design team in a semiconductor design company
In depth user knowledge of one or more of the following tools any SystemC simulator, ARM MaxSim and IP generation tools (for AXI bus etc); Synopsys Discovery Platform, CoreAssembler; Cadence Incisive tools; Mentor PlatformExpress, Seamless technology
Good understanding of Verilog/VHDL hardware description languages
ASIC/SoC design experience using Cadence, Synopsys modeling/verification/synthesis tools
Proficient in scripting languages such as Perl, Tcl.
Knowledge and understanding of back-end chip design flows
Self motivated. Requires minimal supervision and direction.
Results oriented. Can focus on specific objectives and drive toward closure.
Interacts well with others and works toward a common goal. A team player.
Good understanding of the sales cycle and the AE role in it.
Works well under pressure and can adapt to frequently-stressful situations.
Good command of the English language (both oral and written), courteous manners, and ability to promote Atrenta products and corporate image through confidence, attention to detail, and reliability
Overnight travel will be requiredReference Code: Atrenta HR

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